Modern design of integrated circuits (ICs) is a highly structured process based on an HDL (Hardware Description Language) methodology. FIG. 1 illustrates a simplified exemplary flowchart representation of an IC design cycle. First, in step 102 the IC to be designed is specified by a specification document.
Then, the IC design is reduced to an HDL code in step 104. This level of design abstraction is referred to as the Registered Transfer Level (RTL), and is typically implemented using a HDL language such as Verilog-HDL (“Verilog”) or VHDL. At the RTL level of abstraction, the IC design is specified by describing the operations that are performed on data as it flows between circuit inputs, outputs, and clocked registers. The RTL level description is referred to as the RTL code, which is generally written in Verilog or in VHDL.
Next, in step 106 the IC design, as expressed by the RTL code, is synthesized to generate a gate-level description, or a netlist. Synthesis is the step taken to translate the architectural and functional descriptions of the design, represented by RTL code, to a lower level of representation of the design such as a logic-level and gate-level descriptions. The IC design specification and the RTL code are technology independent. That is, the specification and the RTL code do not specify the exact gates or logic devices to be used to implement the design. However, the gate-level description of the IC design is technology dependent. This is because, during the synthesis process, the synthesis tool uses a given technology library 108 to map the technology independent RTL code into technology dependent gate-level netlists.
After the synthesis of the design, the gate-level netlist is verified in step 110, the layout of the circuits is determined and tested in step 112, and the IC is fabricated in step 114.
In the synthesis step 106, logic functions described in a RTL code are mapped to physical circuits using the technology cells in the technology library 108. The technology library 108 may include many different technology cells (or physical circuits) to realize a single logic function. For example, the technology library 108 may include many different technology cells to realize the function of a 2-input AND.
Each logic function may be realized by many different combinations of technology cells. For example, a logic function MUX(Z,S,A,B) may be represented as Z=(˜S & A)+(S & B), where˜ represents NOT, & represents AND, and + represents OR. This representation is a combination of 4 logic functions: 1 NOT, 2 ANDs, and 1 OR. Each of the 4 logic functions may be realized by many different technology cells in the technology library 108. Thus, there are a large number of combinations of technology cells to realize the representation Z=(˜S & A)+(S & B). The logic function MUX(Z,S,A,B) has other representations. For example, the logic function MUX(Z,S,A,B) may be represented as Z=(˜S & A)+(˜S & ˜B). This representation contains 6 logic functions: 3 NOTs, 2 ANDs, and 1 OR. Each of the 6 logic functions may be realized by many technology cells in the technology library 108. Thus, there are a large number of combinations of technology cells to realize the representation Z=(˜S & A)+(˜S & ˜B). Therefore, the total number of physical circuits which realize the logic function MUX(Z,S,A,B) may be very large.
Each physical circuit has a number of parameters such as area, delay, load and the like. The set of parameters that describes a physical circuit is defined as a tech-description of the physical circuit. Tech-descriptions of physical circuits for realizing a logic function are defined as a tech-library of the logic function.
In the mapping process, certain physical circuits for realizing a logic function may be preferred because of the goal of the IC design. For example, if the goal is to reduce the area of the physical circuit, the physical circuit optimized over the area may be chosen.
However, since the technology library generally does not include physical circuits optimized over one or more parameters for realizing a randomly defined logic function, the IC designer often spends large amount of time on choosing an appropriate physical circuit to which the logic function is actually mapped. This may result in unacceptable delay in runtime of the mapping process.
Therefore, it is desirable to provide a method for generating a tech-library for a logic function, which tech-library contains tech-descriptions for physical circuits optimized over one or more parameters to realize the logic function.